As the chip feature size goes below 10 nm, integration of copper interconnect is extremely challenging, especially in the aspects of copper barriers and copper seed deposition. It is known that conformal copper seed layer in gap fill is important to the integration of copper electroplating. However, current process copper seed layer deposited from PVD and CVD cannot meet the demanding requirements. Direct copper fill through PVD methods, even with high temperature processes, proves to be as difficult in certain interconnect geometries.
One difficulty of the integration process is that the copper seed layer should be a continuous film. For PVD copper seed process, films are often non-continuous and not conformal on the sidewall of the trench or via. Existing CVD copper films are not conformal and require a higher substrate temperature which leads to agglomeration of copper within trench or via.
Additionally, existing copper films have impurities resulting from the thermal degradation of the metal precursors. A typical copper film may have in the range of 2 to 10 atomic percent carbon and nitrogen.
Therefore, there is a need in the art for methods of depositing a metal film onto a metal surface selectively over a dielectric surface.